The present disclosure relates to semiconductor structures, and particularly to complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) including identical active semiconductor region shapes and a method of manufacturing the same.
A CMOS circuit includes p-type transistors and n-type transistors. If a process integration scheme employing two separate epitaxial deposition processes are employed to form the active semiconductor regions of the p-type transistors and the active semiconductor regions of the n-type transistors, the two epitaxial deposition processes deposit different semiconductor materials that display different faceting characteristics. Thus, the two epitaxial deposition processes form active semiconductor regions having different faceting profiles. The inherent asymmetry in the faceting profiles of the active semiconductor regions for the two types of transistors results in different device parameters such as different parasitic capacitances between the gate electrode and the active semiconductor regions. Thus, p-type transistors and n-type transistors can have different shapes for active semiconductor regions and accompanying differences in other device parameters. In view of this, there exists a need to minimize the differences in the shapes of the active semiconductor regions and related device parameters across p-type transistors and n-type transistors in a CMOS circuit.